Computer systems are typically made up of multiple nodes which are connected together by a system bus which carries information, such as commands, addresses, data, and control signals between the nodes. Examples of the nodes which make up common computer configurations include central processing units, main memory, and I/0 adapters/controllers, which provide interfaces to mass storage devices and networks. When information is transferred over a bus the receiving node will inform the transmitting node whether that information was corrupted during transmission and whether there were any other protocol errors resulting from the transaction. In part, this is accomplished by checking parity bits, which are transferred along with the information.
When the receiving node has confirmed that the transmission is error-free, it will send back an acknowledgment ("ACK") signal to the transmitting node indicating that the information is good. Alternatively, if the information has been corrupted in transmission or any other bus protocol error occurs, the transmitting node does not return an ACK. This failure to return an ACK during the time period required by the bus protocol is logically understood by the transmitting node as a `no-acknowledgment` ("NACK") signal indicating that the information is not good, and the transmitting node must once again transmit that information.
There is some time delay between the completed transmission of the information to the receiving node, and the determination by the receiving node whether the information was corrupted during transmission and whether there were any other protocol errors. This is because there must be some time for the information to be checked against the parity bit by the bus interface of the receiving node. Thus, if the transmitting node sends information during a first bus cycle, it is common for that node to wait some number of bus cycles before it has an ACK or NACK informing it whether that information is good.
System designs known in the computer architecture art often employ the use of queues for the temporary storage of information which is bound for transmission from one node to another. In a typical implementation, a queue is positioned between a CPU and the interface to the system bus. The CPU will load the queue with information that is to be transferred from the CPU to main memory. An advantage of using the queue in this fashion is that it enhances CPU performance by allowing the CPU to continue processing additional operations before the actual completion of the transfer to main memory. In addition, in the typical implementation the loading of the queue takes place at the same rate at which the CPU operates, which is necessary for maximum performance. The amount of information stored by a output queue is usually sufficient to comprise several transactions. Therefore, a CPU which has a queue is capable of issuing multiple, immediately successive transactions on the system bus as the queue is unloaded.
Although an output queue can issue such multiple, immediately successive transactions, the conventional approach to unloading a queue does not take advantage of this capability because of the need of the system to recover from transmission and bus protocol errors. Specifically, when a NACK results from a given transaction, the system must be able to reissue the transaction so that the information is once again sent from the transmitting node to the receiving node. This conventional approach requires that no successive transaction be commenced until there has been a successful completion of the preceding transaction, or until continuous unsuccessful attempts at transmission of the same information result in a terminating error, known as a "time out".
If, for example, the transmitting node were to commence a second transaction before receiving all of the error information relating to the first transaction, and the first transaction results in an error, the control sub-system of the transmitting node will have to jump back and retransmit the first transaction after transmitting the second transaction. Then, assuming the second transaction is error-free, after the repeated execution of the first transaction, the control sub-system would have to jump ahead to the third transaction, given that there is no need to repeat the second transaction, which was successful. Such a jump back - jump ahead scheme has proven extremely complex, and therefore has not been implemented.
Accordingly, under the conventional unload method, when the information contained in the first queue entry address is transmitted, the system will wait until all of the ACK's have been returned before transmitting the information contained in the second queue entry address. If, however, a NACK is returned, the transaction is repeated. The disadvantage of this approach, however, is that system performance is degraded because the further unloading of the queue is stalled while the node is forced to wait for the ACK's or NACK's relating to a given transaction to be returned. This disadvantage is rather significant in light of the continuing trend for the speed of CPU's to increase, which thereby places a greater demand on system interconnects to issue transactions in an immediately successive order. On the other hand, if the output queue's ability to issue multiple, immediately successive transactions is to be used, the design of the unload system for the queue must be capable of recovering from errors when the original or subsequently attempted transactions result in at least one NACK. Such error recovery capability is a protocol requirement of some advanced system buses.
In accordance with an aspect of the present invention, there is provided a single output queue which is loaded through one set of load circuitry which operates at the same speed as the CPU.
In another aspect of the invention the single output queue is logically divided into two separate logical queues; the two logical queues being made up of those physical queue entry address locations that are even, and those physical queue entry address locations that are odd.
Another aspect of the invention is to access the odd and even queue entry addresses through two separate sets of unload circuitry, which thereby permits rapid unloading of the queue and enhances system performance.
Still another aspect of the invention is to alternate between the unloading of odd and even queue entry addresses so that while one transaction is underway, the immediately preceding transaction can check its own error information to determine whether it should resend the information in the same queue entry address again, or proceed to the next queue entry address. Moreover, this determination by the first half of the logical queue is done independent of the transaction issuance state of the other half of the logical queue. Therefore, the dual access system permits unloading at high performance, but also provides a sophisticated method of error recovery which is practical to implement.